---------------------------------------------------------------------------------
  -- Design Name : work.UserPkg.GenReg32 Test Bench
  -- File Name   : GenReg32.vht
  -- Function    : work.UserPkg.GenReg32 test bench
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use work.TBPkg.all;
use work.UserPkg.all;

entity GenReg32_vhd_tst is
  -- this page is intentionally left blank
end GenReg32_vhd_tst;

architecture GenReg32_arch of GenReg32_vhd_tst is
  -- constants
  -- signals
  signal clk      : std_logic;
  signal ld       : std_logic;
  signal cl       : std_logic;
  signal regIn    : Word32;
  signal regOut   : Word32;
begin
  
  Clock_inst : Clock port map (
    clk => clk
  );
  
  GenReg32_inst : GenReg32 port map (
    -- list connections between master ports and signals
    clk => clk,
    cl => cl,
    ld => ld,
    regIn => regIn,
    regOut => regOut
  );
  
  init : process
  -- variable declarations
  begin
    -- code that executes only once
    -- report "Test bench initialization...";
    -- wait for 25 ps;
    -- ld <= '1';
    -- cl <= '0';
    -- regIn <= "00000000000000000000000000000100";
    -- report "...done";
    wait;                                 -- stop running
  end process init;
  
  always : process
    -- optional sensitivity list
    -- (        )
    -- variable declarations
    variable errCount   : integer := 0;
    variable clkCount   : integer := 0;
    variable test       : boolean := false;
    variable testRegIn  : Word32;
    variable testRegOut : Word32;
  begin
    -- code executes for every event on sensitivity list
    report "Testing...";
    wait for DELAY; 
    for clkCount in 0 to 4 loop
      case clkCount mod 5 is
        -- Test #1
        when 0 => 
          ld <= '1';
          cl <= '0';
          testRegIn := "00000000000000000000000000000100";
          testRegOut := testRegIn;
          regIn <= testRegIn;
        -- Test #2
        when 1 => 
          ld <= '1';
          cl <= '0';
          testRegIn := "10000000000001000000000000110000";
          testRegOut := testRegIn;
          regIn <= testRegIn;
        -- Test #3
        when 2 => 
          ld <= '0';
          cl <= '1';
          testRegIn := "00000000000000000000000000000100";
          testRegOut := (others => '0');
          regIn <= testRegIn;
        -- Test #4
        when 3 =>
          ld <= '1';
          cl <= '1';
          testRegIn := "00000000000000000000000000000101";
          testRegOut := (others => '0');
          regIn <= testRegIn;
        -- Test #5
        when others =>
          ld <= '0';
          cl <= '0';
          testRegIn := "00000000000000000000000111111111";
          --testRegOut := testRegOut;
          regIn <= testRegIn;
      end case;
      wait for CLOCK_PERIOD;
      test := (regOut = testRegOut);
      assert test report "Test failed" severity error;
      if not test then
        errCount := errCount + 1;
      end if;
    end loop;
    
    assert false report "Testing done." severity failure;
    wait;                                 -- stop running
  end process always;
end GenReg32_arch;

configuration GenReg32_vhd_cfg of GenReg32_vhd_tst is 
	for GenReg32_arch
    -- this page is intentionally left blank too
	end for;
end GenReg32_vhd_cfg;